1. Field of the Invention
The present invention relates to a loop type clock adjustment circuit such as a DLL (Delay Locked Loop), PLL (Phase Locked Loop), etc., configured to adjust the phase or the frequency of a clock by making a comparison between the generated clock and a reference clock.
2. Description of the Related Art
A clock adjustment circuit such as a DLL, PLL, etc., includes a clock generating unit (clock adjustment unit) such as a variable delay circuit, a voltage controlled oscillator (which will be referred to as a “VCO” hereafter), or the like, a phase detection unit configured to detect the phase difference between the generated clock and a reference clock, and a loop control circuit configured to perform feedback control of the clock generating unit according to the phase difference.
The phase detection unit makes a comparison between the phases of the two clocks, and generates a phase difference signal that switches between high level and low level according to the phase difference. Specifically, the signal level switches according to the forward phase or the reverse phase.
Here, we consider an arrangement in which the loop control circuit has a configuration comprising: a counter configured to count up or count down according to the phase difference signal; and a digital/analog conversion circuit (DAC) configured to perform digital/analog conversion of the count value of the counter so as to control the clock generating unit.
In a case of employing a binary counter as such a counter, when a carry or a borrow occurs, in some cases, a transition with a large Hamming distance occurs. In a case in which a transition with a large Hamming distance occurs, multiple flip-flops included within the counter transit at the same time, leading to a problem of noise occurring in the counter. Furthermore, the value of each bit of the counter corresponds to the ON/OFF operation of the corresponding switch included in the DAC provided as a downstream component. In some cases, this leads to noise occurring in the DAC provided as a downstream component. For example, when the counter counts up and transits from the state [01111] to the state [10000] (states are represented as binary values), due to time lag that occurs in the transition operation of each switch, the counter temporarily transits from level 15 (=[01111]) to level 0 (=[00000]), following which the counter transits to level 16 (=[10000]). Alternatively, in some cases, the counter transits in the order level 15, level 31, level 16 ([01111], [11111], [10000]). This leads to a problem of noise being superimposed on the output of the DAC.
In order to solve such a problem, a method is conceived that employs a counter using a thermometer code. With such an arrangement, counting up and counting down are performed with a Hamming distance of 1 using the thermometer code. Thus, such an arrangement provides reduced switching noise as compared with an arrangement employing a binary counter. However, such an arrangement requires that the number of bits correspond to the maximum level of the count value. Accordingly, there is a need to provide data holding circuits such as flip-flops or latch circuits corresponding to the number of bits, leading to a problem of an increased circuit area.